Overviews
　　The ultimate goal of radar and sonar application is to detect, estimate and track the target. Its task is to process the received signal, extract the features, analyze and identify the target, in order to detect the presence or absence of the target, then through the signal processing and operation to estimate the direction of the target, distance and speed, to achieve positioning and tracking.

In the information and electronic modern war, radar/sonar system is playing more and more important role, also has higher and newer request. Advanced Signal processing capability is needed to network radar/sonar systems with different functions, and multi-sensor information fusion is needed to achieve functional complementarity and resource sharing. RADAR/SONAR system needs to collect a large amount of data to detect, classify and locate signals, but due to the limitation of data transmission bandwidth, it often needs to compress data, which leads to a large amount of data loss and high delay. Therefore, the adoption of new bus and system architecture technology is particularly important.

Scheme design
　　The radar/sonar signal processing system is based on VXS or OpenVPX system. The system adopts RapidIO interconnect bus technology with high bandwidth and low delay. The system is a fully integrated RapidIO multi-computer system, the full-fledged multi-processor parallel software development environment and high-performance RapidIO switch, POWERPC 8640D/8641D multi-processor computing module, large-scale FPGA computing module, multi-channel ADC data acquisition module, all kinds of i/o functional modules are fully integrated, in addition, we can integrate third-party products such as Fiber Channel Channel Card, AFDX, 1553, image display module and so on. In addition, we can also integrate high-performance digital receiver products in the system for users to meet the harsh high-frequency data acquisition and large-scale in-board FPGA frequency reduction applications. This solution can meet the requirements of harsh signal processing, image processing, data fusion and data transmission tasks for radar/sonar, SIGINT and ELINT applications.

Scheme Diagram

系统方案组成典型解决方案图

Logic function diagram of system scheme composition

Technical Specification

HPEC 6000 system:

　　◇ Up to 70 processors, 756 GFLOPS

　　◇ RapidIO switching architecture, 42gb/s inter-processor bandwidth

　　◇ Dual processor or quad-processor POWERPC 8640D/8641D processor module

　　◇ FPGA computing module based on FMC

　　◇ Digital Receiver based on large-scale FPGA

　　◇ Rich i/o options

　　◇Powerful multi-processor parallel application development software

Application area
　　◇Airborne radar signal processing system

　　◇ Shipborne radar signal processing system

　　◇ Sonar signal processing system

　　◇ ……

Category: Electronic System Simulation